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Bit
2
Name
HFXOEN
Reset
0
Access
W1
Description
HFXO Enable
Enables the HFXO.
1
HFRCODIS
0
W1
HFRCO Disable
Disables the HFRCO. HFRCOEN has higher priority if written simultaneously. WARNING: Do not disable the HFRCO if this oscillator
is selected as the source for HFCLK.
0
HFRCOEN
0
W1
HFRCO Enable
Enables the HFRCO.
11.5.10 CMU_CMD - Command Register
Offset
0x024
Reset
Access
Name
Bit Position
Bit
Name
Reset
Access
Description
31:4
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
3
CALSTART
0
W1
Calibration Start
Starts the calibration, effectively loading the CMU_CALCNT into the down-counter and start decrementing.
2:0
HFCLKSEL
0x0
W1
HFCLK Select
Selects the clock source for HFCLK. Note that selecting an oscillator that is disabled will cause the system clock to stop. Check the
status register and confirm that oscillator is ready before switching.
Value
1
2
3
4
Mode
HFRCO
HFXO
LFRCO
LFXO
Description
Select HFRCO as HFCLK
Select HFXO as HFCLK
Select LFRCO as HFCLK
Select LFXO as HFCLK
11.5.11 CMU_LFCLKSEL - Low Frequency Clock Select Register
Offset
0x028
Reset
Access
Name
Bit Position
Bit
Name
Reset
Access
Description
31:4
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
3:2
LFB
0x1
RW
Clock Select for LFB
Selects the clock source for LFBCLK
Value
0
Mode
DISABLED
Description
LFBCLK is disabled
2011-04-12 - d0001_Rev1.10
108
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